A conventional typical semiconductor package includes recess portions (hereinafter, referred to as semiconductor-element receiving cavities or cavities in some cases) for receiving semiconductor elements and through holes rendering respective electrode layers conductive.
Typical processes are as follows:
Process 0: form cavity holes and circuits in a plate (hereinafter, an insulating sheet) made of an insulating material
Process 1: stack the insulating sheet formed in Process 0 and an adhesive layer
Process 2: drill through holes
Process 3: plate through holes and bottom and top surfaces of the stacked body
Process 4: remove unnecessary plated portions of the bottom and top surfaces of the stacked body by etching
Process 5: apply and pattern a solder resist
Process 6: plate with gold
Process 7: singulate by dicing
However, there is a problem in that, when the through holes are plated, a plating layer adheres to the whole semiconductor-element receiving cavities; therefore, the electrodes, such as die bonding electrodes on which semiconductor elements are to be mounted and wire bonding electrodes, are short-circuited.
The following technology is disclosed in Patent Literature 1. In Patent Literature 1, a technology is proposed in that, when the through holes and the bottom and top surfaces of the stacked body are plated in Process 3 described above, in order to avoid plating from adhering to the semiconductor-element receiving cavities, the semiconductor-element receiving cavities are sealed with an insulating sheet and, after the plating process is finished, part of the insulating sheet is removed as Process 4 so as to form the semiconductor-element receiving cavities. Thereafter, singulation is performed by dicing.